87. 4-bit Bidirectional Shift Register

How do you plan to solve it?

a bidirectional shift register

module shift_reg_bidirectional (
    input        CLK,
    input        RST,
    input        DIR,
    input        serial_in,
    output reg [3:0] Q
);
    // Write your code here
    always @(posedge CLK) begin
        if (RST)
            Q <= 4'd0;
        else
            Q <= DIR ? ({Q[2:0], serial_in}) : ({serial_in, Q[3:1]});
    end
    
endmodule