87. 4-bit Bidirectional Shift Register

How do you plan to solve it?

module shift_reg_bidirectional (
    input        CLK,
    input        RST,
    input        DIR,
    input        serial_in,
    output reg [3:0] Q
);
    // Write your code here
    always @(posedge CLK or posedge RST) begin 
        if (RST) Q <= 0;
        else Q <= DIR ? ((Q << 1) | serial_in) : ((Q >> 1) | {serial_in,3'b0});
    end
endmodule