87. 4-bit Bidirectional Shift Register

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hiung

Solving Approach

How do you plan to solve it?

Code

module shift_reg_bidirectional (
    input        CLK,
    input        RST,
    input        DIR,
    input        serial_in,
    output reg [3:0] Q
);
    // Write your code here
    always @ (posedge CLK or posedge RST) begin
        if ( RST ) Q <= 0;
        else begin
            Q <= DIR ? {Q[2:0],serial_in} : {serial_in,Q[3:1]};
        end
    end
endmodule

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