87. 4-bit Bidirectional Shift Register

How do you plan to solve it?

module shift_reg_bidirectional (
    input        CLK,
    input        RST,
    input        DIR,
    input        serial_in,
    output reg [3:0] Q
);
    // Write your code here
    always @ (posedge CLK or posedge RST) begin
        if(!RST) begin
            Q <= DIR ? ( (Q<<1) | (4'b0001 & {4{serial_in}})) : ((Q>>1) | (4'b1000 & {4{serial_in}}));
        end else begin
            Q <= 4'b0000;
        end
    end
    
endmodule