86. 4-bit Register with Synchronous Reset

How do you plan to solve it?

module reg4_sync_reset (
    input        CLK,
    input        RST,
    input  [3:0] D,
    output reg [3:0] Q
);
// Write your code here
    always @(posedge CLK) begin
        if(RST==1'b1) begin
            Q<=4'b0000;
        end
        else begin
            Q<=D;
        end
    end
endmodule