86. 4-bit Register with Synchronous Reset

How do you plan to solve it?

module reg4_sync_reset (
    input        CLK,
    input        RST,
    input  [3:0] D,
    output reg [3:0] Q
);
 always @ (posedge CLK or posedge RST)begin
    if (RST)
      Q=4'b0000;
    else
      Q <= D;
 end
// Write your code here

endmodule