86. 4-bit Register with Synchronous Reset

How do you plan to solve it?

• Synchronous reset is sampled at the rising edge; changes between edges do not affect Q until the next edge.
• First priority to the RST and then to the data.
• As it is sequential ckt the non-blocking statement is used here.

module reg4_sync_reset (
    input        CLK,
    input        RST,
    input  [3:0] D,
    output reg [3:0] Q
);
// Write your code here

always@(posedge CLK) begin
    if(RST)
        Q <= 4'b0000;
    else
        Q <= D;

end

endmodule