86. 4-bit Register with Synchronous Reset

How do you plan to solve it?

module reg4_sync_reset (
    input  wire        CLK,
    input  wire        RST,
    input  wire [3:0]  D,
    output reg  [3:0]  Q
);

always @(posedge CLK) begin
    if (RST)
        Q <= 4'b0000;   // synchronous reset
    else
        Q <= D;         // normal load
end

endmodule