85. 4-bit Register

module reg4 (
    input	CLK,
    input	[3:0] D,
    output	reg [3:0] Q
);
    always @(posedge CLK) begin
        Q <= D;
    end
endmodule

💡Remember

• Use nonblocking assignments for sequential storage.
• With no reset, power-up is unknown; the first rising edge defines Q.