74. 4-bit Register

Testbench Code

`timescale 1ns/1ps

module tb_reg4;
    // 1) Inputs
    reg        CLK;
    reg  [3:0] D;
    // 2) Outputs
    wire [3:0] Q;
    // 3) Expected outputs (prefixed "expected_")
    reg  [3:0] expected_Q;
    // 4) Mismatch (HIGH when outputs != expected)
    wire mismatch;

    // DUT
    reg4 dut(.CLK(CLK), .D(D), .Q(Q));

    // Scoreboard: mirror DUT capture at posedge
    always @(posedge CLK) expected_Q <= D;

    // 4-state aware compare
    assign mismatch = (Q !== expected_Q);

    // Counters / limits
    integer TOTAL_TEST_CASES        = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;
    integer VCD_MAX_CASES           = 32;
    integer ERROR_MAX_CASES         = 32;

    integer i, j;

    // Free-running clock (10 time-unit period)
    initial begin
        CLK = 1'b0;
        forever #5 CLK = ~CLK;
    end

    // VCD — order: Inputs -> Outputs -> Expected -> mismatch; start at #0
    initial begin
        $dumpfile("tb_reg4.vcd");
        $dumpvars(0,
            tb_reg4.CLK,
            tb_reg4.D,
            tb_reg4.Q,
            tb_reg4.expected_Q,
            tb_reg4.mismatch
        );
        $dumpon;
    end

    // Drive D on negedge; check after next posedge
    task drive_and_check;
        input [3:0] d_val;
    begin
        @(negedge CLK);
        D = d_val;
        @(posedge CLK); #1;

        TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
        if (!mismatch) begin
            TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
        end else begin
            TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;
            if (TOTAL_FAILED_TEST_CASES <= ERROR_MAX_CASES)
                $display("[FAIL] D=0x%1h  Q=0x%1h expected_Q=0x%1h  t=%0t",
                         D, Q, expected_Q, $time);
        end
        if (TOTAL_TEST_CASES == VCD_MAX_CASES) $dumpoff;
    end
    endtask

    // Between-edge change (no check; Q must hold until next edge)
    task change_between_edges;
        input [3:0] d_val;
    begin
        @(negedge CLK);
        D = d_val;
    end
    endtask

    initial begin
        // Start unknown like real silicon; first edge defines it
        D = 4'b0000; expected_Q = 4'bx;
        @(posedge CLK); #1;

        // Directed captures
        drive_and_check(4'h0);
        drive_and_check(4'h5);
        drive_and_check(4'hF);

        // Demonstrate hold between edges
        change_between_edges(4'h9);
        drive_and_check(4'h9);
        drive_and_check(4'h3);

        // Exhaustive two-step over 4-bit values (trimmed)
        for (i=0; i<4; i=i+1) begin
            drive_and_check(i[3:0]);
            for (j=0; j<4; j=j+1)
                drive_and_check(j[3:0]);
        end

        // Random stress
        for (i=0; i<10; i=i+1)
            drive_and_check($random);

        // Summary
        $display("TOTAL_TEST_CASES=%0d",        TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",    (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");

        #2 $finish;
    end
endmodule