78. D Flip-Flop with Asynchronous Reset

module dff_async_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);
    always @(posedge CLK or posedge RST) begin
        if (RST)
            Q <= 1'b0;
        else
            Q <= D;
    end
endmodule

💡Remember

• Asynchronous reset acts immediately; include posedge RST in the sensitivity list.
• Reset dominates data; while asserted, clock edges do not change Q.
• Use nonblocking assignments inside the clock/reset block.
• Release of async reset should be timed carefully in real hardware; data captures resume on the next rising clock edge after RST=0.