78. D Flip-Flop with Asynchronous Reset

How do you plan to solve it?

module dff_async_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);
    always @(posedge CLK or posedge RST) 
    if (RST) begin 
        Q <=0;
    end 
    else 
       Q <=D;
    
endmodule