78. D Flip-Flop with Asynchronous Reset

How do you plan to solve it?

The always block doesn't actually performs so you need to write code for it in case statement. Also, the changes based on the clock edge as well as the reset.

module dff_async_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);
    // async active-high reset with posedge sensitivity
    always @(posedge CLK or posedge RST) begin
        if(RST)
            Q = 1'b0;
        else
            Q <= D;
    end

endmodule