78. D Flip-Flop with Asynchronous Reset

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RamikshaShetty

November 3, 2025

Solving Approach

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Code

module dff_async_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);
always @(posedge CLK or posedge RST) begin
    if(RST) begin
        Q <= 1'd0;
    end
    else Q <= D;
end
    // async active-high reset with posedge sensitivity
    
endmodule

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