78. D Flip-Flop with Asynchronous Reset

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RijeshThayathidath

RijeshThayathidath

January 3, 2026

Solving Approach

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Code

module dff_async_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);
    // async active-high reset with posedge sensitivity
    always @(posedge CLK or posedge RST) begin
      if(RST) begin
        Q<=0;
      end
      else begin
        Q<=D;
      end
    end
    
endmodule

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