78. D Flip-Flop with Asynchronous Reset

How do you plan to solve it?

module dff_async_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);
    always@(posedge RST or posedge CLK)begin
        if(RST) Q <= 0;
        else Q <= D;
    end
    
endmodule