78. D Flip-Flop with Asynchronous Reset

How do you plan to solve it?

module dff_async_reset(CLK,RST,D,Q);
input CLK;
input RST;
input D;
output reg Q;

always @(posedge CLK or posedge RST)
begin
    if(RST)
    Q<=1'b0;
    else
    Q<=D;
end
endmodule