77. D Flip-Flop

How do you plan to solve it?

At every posedge  we are updating the output with input.

module dff_posedge (
    input  CLK,
    input  D,
    output reg Q
);
    // capture D on each rising edge of CLK
    always@(posedge CLK)begin
        Q <= D;

    end
endmodule