77. D Flip-Flop

How do you plan to solve it?

module dff_posedge (
    input  CLK,
    input  D,
    output reg Q
);
    // capture D on each rising edge of CLK
    always @(*) begin
        case (CLK)
        1'b1: Q=D;
        1'b0: Q=Q;
       
        endcase
    end
endmodule