77. D Flip-Flop

How do you plan to solve it?

module dff_posedge (
    input  CLK,
    input  D,
    output reg Q
);
    // capture D on each rising edge of CLK
always @(posedge CLK)begin
    if(D)begin
        Q = 1'b1;
    end
    else begin
        Q = 1'b0;
    end
end
endmodule