76. D Latch with Enable-Synchronous Reset

How do you plan to solve it?

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);
    always @ (*) begin
        if (!EN) begin
            Q=Q;
        end else begin
            if(RST)begin
                Q=0;
            end else begin
                Q=D;
            end
        end
    end
    
endmodule