76. D Latch with Enable-Synchronous Reset

How do you plan to solve it?

module d_latch_en_sync_reset (
    input  EN,
    input  RST,   // synchronous to EN (not clock!)
    input  D,
    output reg Q
);

always @(*) begin
    if (EN) begin
        if (RST)
            Q = 1'b0;     // reset only works when EN=1
        else
            Q = D;        // normal latch behaviour
    end
    // else: Q holds value automatically
end

endmodule