76. D Latch with Enable-Synchronous Reset

How do you plan to solve it?

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);
    // Write your code here
    always@(*)
    begin
        if(RST == 1 && EN == 1)
            Q <= 0;
        else if (RST == 0 && EN == 1)
            Q <= D;
        else if (EN == 0 )
            Q <= Q ; 
    end
    
endmodule