76. D Latch with Enable-Synchronous Reset

How do you plan to solve it?

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);
    always @(*)begin
        if(RST && EN)begin
            Q<=1'b0;
        end
        else if(EN && !RST)begin
        Q<=D;
        end
        else begin
        Q<=Q;
    end

    end
    
endmodule