76. D Latch with Enable-Synchronous Reset

How do you plan to solve it?

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);
    // Write your code here
    always@(*)begin
    if(EN)begin
       if(RST) Q=1'b0;
       else Q=D;
    end  
    else Q=Q;
    end
    
endmodule