76. D Latch with Enable-Synchronous Reset

How do you plan to solve it?

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);
always@(*) begin
    if(EN==0)
    Q<=Q;
    else if(EN==1 && RST==1)
    Q<=0;
    else if(EN==1 && RST==0)
    Q<=D;
end

    
endmodule