76. D Latch with Enable-Synchronous Reset

How do you plan to solve it?

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);

always@* begin
    if (EN && RST)
    Q=1'b0;

    else if(EN && (~RST))
    Q=D;

    else
    Q=Q;
end
    // Write your code here
    
endmodule