76. D Latch with Enable-Synchronous Reset

How do you plan to solve it?

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);

always @(EN or RST or D) begin

    // Latch transparent only when EN=1
    if (EN) begin

        // Reset active only during transparency
        if (RST)
            Q <= 1'b0;

        else
            Q <= D;
    end

    // EN=0:
    // no assignment -> hold previous value

end

endmodule