76. D Latch with Enable-Synchronous Reset

How do you plan to solve it?

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);
    // Write your code here
    always@(EN or D or RST)begin
        if(EN)
            if(!RST)
            Q <= D;
            else if(RST)
            Q <= 1'b0;
        else if(!EN)
            Q <= Q;
    end
    
endmodule