76. D Latch with Enable-Synchronous Reset

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);
    // Write your code here
    always @(*) begin
        if(EN) begin
            if(RST) begin
                Q = 0;
            end
            else begin
                Q = D;
            end
        end
        else begin
            Q = Q;
        end
    end
endmodule