76. D Latch with Enable-Synchronous Reset

How do you plan to solve it?

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);
    always @(*)begin
        if(EN)begin
        if(RST)
        Q=1'b0;
        else 
        Q=D;
    end
    else begin
        Q=Q;
    end
    end
endmodule