76. D Latch with Enable-Synchronous Reset

How do you plan to solve it?

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);
    // Write your code here
    always @(*) begin
        case (EN)
        1'b1: Q=((RST==0)?D:0);
        1'b0: Q=Q;
        endcase
    end
endmodule