76. D Latch with Enable-Synchronous Reset

How do you plan to solve it?

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);
    // Write your code here
    always @(EN or RST or D)begin
        if(EN==1)
           begin
            if(RST==1)
              Q <= 0;
            else
              Q = D;
           end
        else
         Q <= Q;
    end
    
endmodule