76. D Latch with Enable-Synchronous Reset

How do you plan to solve it?

module d_latch_en_sync_reset (
    input  EN,
    input  RST,
    input  D,
    output reg Q
);
    // Write your code here

    reg qi;

    always @* begin

        if(EN) begin
            if(RST) qi = 0;
            else qi = D;
        end else qi = Q;

        Q = qi;
    end
    
endmodule