80. DFF with Async Reset and Preset

How do you plan to solve it?

module dff_async_reset_preset (
    input  CLK,
    input  RST,
    input  PRE,
    input  D,
    output reg Q
);  
always @(posedge CLK or posedge PRE or posedge RST )begin
    if (RST)
        Q <= 1'b0;
    else if(PRE)
        Q <= 1'b1;
    else Q <= D;

end



endmodule