module dff_async_reset_preset (
input CLK,
input RST,
input PRE,
input D,
output reg Q
);
always @(posedge CLK, posedge RST, posedge PRE ) begin
if (RST) begin
Q <= 0;
end else begin
if (PRE) begin
Q <= 1;
end else begin
Q <= D;
end
end
end
endmodule