How do you plan to solve it?
module dff_async_reset_preset ( input CLK, input RST, input PRE, input D, output reg Q ); always@(posedge CLK or posedge RST or posedge PRE) begin if(RST==1) begin Q<=1'b0; end else if(PRE==1) begin Q<=1'b1; end else begin Q<=D; end end endmodule