80. DFF with Async Reset and Preset

How do you plan to solve it?

module dff_async_reset_preset (
    input  CLK,
    input  RST,
    input  PRE,
    input  D,
    output reg Q
);

    always @(posedge RST or posedge PRE or posedge CLK) begin
        if (RST) begin
            Q <= 1'b0;
        end else if (PRE) begin
            Q <= 1'b1;
        end else begin
            Q <= D;
        end
    end


endmodule