80. DFF with Async Reset and Preset

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RijeshThayathidath

RijeshThayathidath

January 3, 2026

Solving Approach

How do you plan to solve it?

Code

module dff_async_reset_preset (
    input  CLK,
    input  RST,
    input  PRE,
    input  D,
    output reg Q
);

always @(posedge CLK or posedge RST or posedge PRE) begin
    if(RST) begin
        Q<=0;
    end
    else if(PRE) begin
        Q<=1;
    end
    else begin
        Q<=D;
    end
end


endmodule

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