80. DFF with Async Reset and Preset

How do you plan to solve it?

module dff_async_reset_preset (
    input  CLK,   // Clock input (positive-edge triggered)
    input  RST,   // Asynchronous active-high reset
    input  PRE,   // Asynchronous active-high preset
    input  D,     // Data input
    output reg Q  // Output
);
    // Asynchronous control: responds to reset/preset immediately,
    // otherwise normal D flip-flop on rising edge of clock
    always @(posedge CLK or posedge RST or posedge PRE) begin
        if (RST)
            Q <= 1'b0;          // Highest priority: reset forces Q=0
        else if (PRE)
            Q <= 1'b1;          // Next priority: preset forces Q=1
        else
            Q <= D;             // Otherwise, capture D on rising CLK
    end
endmodule