80. DFF with Async Reset and Preset

How do you plan to solve it?

module dff_async_reset_preset (
    input  CLK,
    input  RST,
    input  PRE,
    input  D,
    output reg Q
);
     always@(posedge CLK, posedge RST, posedge PRE)
    if(RST==1)
    begin
        Q<=0;
    end
    else
    begin
        if(PRE==1)
        begin
            Q<=1;
        end
        else
        begin
        Q<=D;
        end
    end

endmodule