80. DFF with Async Reset and Preset

All Submissions

Shradha

Solving Approach

How do you plan to solve it?

Code

module dff_async_reset_preset (
    input  CLK,
    input  RST,
    input  PRE,
    input  D,
    output reg Q
);
always@(posedge CLK or posedge RST or posedge PRE)begin
    if (RST)
    Q<= 1'b0;
    else if (PRE)
    Q<= 1'b1;
    else
    Q<= D;
end

endmodule

Was this helpful?