80. DFF with Async Reset and Preset

How do you plan to solve it?

module dff_async_reset_preset (
    input  CLK,
    input  RST,   // asynchronous reset (active high)
    input  PRE,   // asynchronous preset (active high)
    input  D,
    output reg Q
);
    always @(posedge CLK or posedge RST or posedge PRE) begin
        if (RST)
            Q <= 1'b0;      // asynchronous reset
        else if (PRE)
            Q <= 1'b1;      // asynchronous preset
        else
            Q <= D;         // normal clocked behavior
    end
endmodule