80. DFF with Async Reset and Preset

How do you plan to solve it?

module dff_async_reset_preset (
    input  CLK,
    input  RST,
    input  PRE,
    input  D,
    output reg Q
);
always @(posedge CLK or posedge RST or posedge PRE)begin
    //if(RST) Q <=0;
    //else if(PRE) Q <=1;
    //else Q <=D;
    Q <=    (RST)? 0:
            (PRE)? 1: D;
end

endmodule