79. DFF with Synchronous Reset

module dff_sync_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);
    always @(posedge CLK) begin
        if (RST)
            Q <= 1'b0;
        else
            Q <= D;
    end
endmodule

💡Remember

• Synchronous reset is evaluated at the active clock edge; changes between edges don’t affect Q until the next edge.
• Give reset priority over data inside the clocked block.
• Use nonblocking assignments in sequential blocks.
• Drive D/RST on the opposite clock phase in the testbench to meet setup.