10. Half Adder Design
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- Minterm Extraction: Analysing the two output columns individually shows that Output Sum is active high at rows 01 and 10, which matches an exclusive-OR behavior. Output Carry is active high only at row 11, which matches an AND behavior.
- K-Map Optimization: Plotting the separate outputs onto 2-variable Karnaugh maps reveals that no cell combinations can be formed. The individual targets establish standalone functional primitives directly.
- Minimized SOP Expression: The optimized circuit configurations decouple into two separate expressions:
- Output Sum = Input A XOR Input B, and
- Output Carry = Input A AND Input B.
- Structural Hardware Mapping: Input A and Input B fan out in parallel to drive both processing blocks simultaneously. Gate Xor1 evaluates the data lines to solve the Output Sum channel, while gate And1 evaluates the identical data lines to solve the Output Carry channel.