/*module jk_ff (
input CLK,
input J,
input K,
output reg Q
);
always @(posedge CLK) begin
if (J==0 && K==0) Q <= Q;
else if (J==0 && K==1) Q <= 0;
else if (J==1 && K==0) Q <= 1;
else Q <= ~Q;
end
endmodule*/
module jk_ff (
input CLK,
input J,
input K,
output reg Q
);
always @(posedge CLK) begin
case ({J, K})
2'b00: Q <= Q; // hold
2'b01: Q <= 1'b0; // reset
2'b10: Q <= 1'b1; // set
2'b11: Q <= ~Q; // toggle
endcase
end
endmodule