How do you plan to solve it?
module jk_ff ( input CLK, input J, input K, output reg Q ); // Write your code here always@(posedge CLK)begin case({J,K}) 2'b00:Q<=Q; 2'B01:Q<=1'B0; 2'B10:Q<=1'B1; 2'B11:Q<=~Q; endcase end endmodule