How do you plan to solve it?
module jk_ff ( input CLK, input J, input K, output reg Q ); // Write your code here always@(posedge CLK)begin case ({J,K}) 2'b00: Q <=Q; 2'b01: Q <=1'b0; 2'b10: Q <=1'b1; 2'b11: Q <=~Q; endcase end endmodule