81. JK Flip-Flop

How do you plan to solve it?

module jk_ff (
    input  CLK,
    input  J,
    input  K,
    output reg Q
);
// Write your code here
 wire [1:0] sel = {J,K};
    always @(posedge CLK) begin
        case(sel)
        2'd0    : Q <=Q;
        2'd1    : Q <=0;
        2'd2    : Q <=1;
        2'd3    : Q <=~Q;
        endcase
    end
endmodule